1. Field of the Invention
This invention relates to amplifier circuits and, more particularly, to an operational amplifier which can output a voltage near the upper power supply level (e.g., VDD).
2. Description of the Related Art
Amplifiers are often used in integrated circuit design. Even in the case of digital integrated circuits, amplifiers may be used for purposes such as providing a reference voltage for other parts of the circuit. Generally, an amplifier makes use of power from a DC power supply to produce an output signal having its voltage and/or current increased with respect to that of an input signal. Specialized amplifiers known as operational amplifiers exhibit extremely high voltage gain, high input impedance, and low output impedance. Such operational amplifiers are useful in allowing output voltages to be produced which have specific mathematical relationships to input voltages. Operations such as addition, subtraction, multiplication, division, differentiation, and integration can be realized by configuring the operational amplifier with additional circuit elements. For example, a voltage multiplier circuit can be formed using a resistor network with an operational amplifier to multiply a constant factor by an input reference voltage. In this way, a voltage reference can be made for use in an integrated circuit.
To accurately produce a desired output voltage using an operational amplifier, however, requires that the amplifier have good AC and DC characteristics. The necessary AC characteristics may include common mode rejection ratio, positive power supply rejection ratio, negative power supply rejection ratio, open loop gain and closed loop gain. The necessary DC characteristics may include high gain and sufficient current drive at the output to maintain the desired output voltage level over the range of load impedances expected. Conditions on integrated circuits are not always conducive to having desirable characteristics for an operational amplifier, however. In particular, the available power supply voltages on integrated circuits are continually being reduced. Such reduction in power supply voltage is used to reduce overall power consumption of the integrated circuit, which may be particularly important for the use of portable and other battery operated devices, and to reduce heating problems caused by increasing circuit density. Early operational amplifiers tended to use power supply voltages of xc2x110 volts or xc2x115 volts. Because of scaling of transistor geometries, however, current integrated circuits typically need power supply voltages ranging from 0 volts at the low end to upper levels as low as 3 volts, 2 volts, or less. In such cases, the external power supply voltage may be only slightly above an internal reference voltage needed for the integrated circuit. Conventional operational amplifier designs tend to show degraded performance when the output voltage needed is near the upper limit of the power supply.
It would therefore be desirable to develop an amplifier circuit with good AC characteristics even when its output voltage is near the upper limit of the power supply voltage. The desired amplifier should also be resistant to the noisy environment which may be encountered on digital integrated circuits.
The problems outlined above may be in large part solved by a method and circuit as described herein. In the method, an output voltage of an amplifier is produced at a level near the power supply voltage of the amplifier. The method may include producing a first stage output voltage ranging to within a transistor turn-on voltage of the power supply voltage. The first stage output voltage may then be coupled to a second stage of the amplifier where the coupling modulates or controls a current flow through a first pair of cascaded transistors within the second stage. The cascaded transistors may particularly be connected in a cascode configuration. The first pair of cascaded transistors may be coupled between an output node carrying the output voltage and a power supply node carrying the power supply voltage. The coupling of the first stage output voltage to the second stage may in one embodiment include coupling the first stage output voltage to an input terminal of a third transistor, where the third transistor is coupled between the power supply node and an additional pair of cascaded transistors. A gate terminal of each transistor from this additional pair of transistors may be coupled to a gate terminal of a corresponding transistor from the first pair of cascaded transistors.
In a further embodiment, the method may include stabilizing the frequency response of the amplifier with a frequency compensation network coupled between the input terminal of the third transistor and an output terminal of the third transistor. In addition to modifying a current flow through a first pair of cascaded transistors as described above, the method may further include modifying a current flow through an additional pair of cascaded transistors which is coupled between the output node and a lower power supply node carrying, e.g., a ground potential. This modification of current flow may be accomplished by coupling an additional first stage output voltage to the second stage. In an embodiment for which the current flow through the first pair of cascaded transistors is reduced, the current through the additional pair of cascaded transistors may be increased. Such an embodiment may result in the output voltage being maintained within 0.2 volts of the power supply voltage. In a further embodiment, the method may include stabilizing the frequency response of the amplifier with a frequency compensation network coupled between the output node and a terminal of one of the pair of transistors coupled between the output node and the power supply node.
An embodiment of an amplifier circuit which may be used to implement a method such as that described above may include a differential first stage coupled to the power supply node and providing a pair of first stage outputs for coupling to a differential second stage. Each of the first stage outputs may be taken at a terminal of a respective transistor having a respective turn-on voltage. A difference between the power supply node voltage during circuit operation and an achievable voltage range of each of the first stage outputs may be less than the turn-on voltage of the respective transistor. This small difference between the power supply node voltage and the achievable voltage range of each first stage output is in contrast to the first stage output voltage ranges of some other amplifier circuits. In particular, some amplifier circuits have load transistors in the first stage constrained to operate in a mode for which the current-voltage characteristics of the transistors are relatively flat. This corresponds to operation within saturation mode for a field effect transistor. A field-effect transistor operates in saturation mode whenever the magnitude of the drain-to-source voltage for the transistor is greater than or equal to the magnitude of the gate-to-source voltage minus the threshold voltage of the transistor.
This constraining of the mode of operation of a transistor may be accomplished in some embodiments by diode-connecting the transistor. For example, the drain and gate of field effect transistor may be tied together, thereby forcing the device to be operated in saturation mode. Although diode-connecting a transistor in this manner may improve the output impedance of a given amplifier stage by forcing it to remain in an operation mode with relatively flat current-voltage characteristics, this practice provides a severe constraint on the output voltage range of the stage. In general, such a constraint forces the difference between the power supply voltage and the output voltage of such a load transistor to be at least a turn-on voltage of the transistor. In the case of a field effect transistor, a turn-on voltage corresponds to a threshold voltage of the transistor. Not diode-connecting the first stage load transistors, on the other hand, may increase the first stage gain and allow good performance even when the output of the entire amplifier is very near the power supply level.
An embodiment of the circuit described above may further include the differential second stage coupled to the power supply node and to the first stage outputs, where the second stage includes an output node and where an achievable output node voltage range during circuit operation extends to within 0.2 volts of the power supply node voltage. The second stage may further include a pair of cascaded transistors coupled between the power supply node and the output node. In an embodiment, the circuit may further include a frequency compensation network coupled between the output node and a terminal of one of the pair of transistors. Alternatively or in addition, the circuit may be adapted to provide a current of at least 50 microamperes through the pair of transistors while the output node voltage is within 0.2 volts of the power supply voltage. In an embodiment of the circuit, one of the pair of first stage outputs may be coupled to a terminal of one of the pair of transistors. The other of the pair of first stage outputs may be coupled to an input terminal of a third transistor which is coupled to the power supply node. In such an embodiment, the circuit may further include a frequency compensation network coupled between the input terminal of the third output stage transistor and an output terminal of the third output stage transistor. The third output stage transistor may further be coupled between the power supply node and a second pair of cascaded transistors. A gate terminal of each transistor from the second pair of output stage transistors may be coupled to a gate terminal of a corresponding transistor from a third pair of transistors coupled between the output node and a ground potential node.
An alternative embodiment of an amplifier circuit may include a power supply node and an output node, where the circuit is adapted to provide during operation an output node voltage ranging to within 0.2 volts of a power supply node voltage used during operation. The circuit may further include a first stage load transistor coupled to the power supply node, where the first stage load transistor is a field effect transistor not constrained by the circuit to operate in a diode-connected fashion. In addition, the circuit may include a pair of cascaded transistors coupled between the power supply node and the output node. In a further embodiment, the circuit may include a frequency compensation network coupled between the output node and a terminal of one of the cascaded transistors. Such a frequency compensation network may include a resistor and a capacitor. In an embodiment, the circuit may be adapted to provide a current of at least 50 microamperes through the pair of transistors, while the output node voltage is within 0.2 volts of the power supply node voltage.